1. Field of the Invention
This disclosure relates to a semiconductor memory devices, and more particularly to power supply circuitry associated with semiconductor memory devices.
2. Description of the Related Art
In some semiconductor memory devices an externally supplied high voltage is converted into a low internal voltage. A semiconductor device such as Metal-Oxide Semiconductor (MOS) transistor can operate with a low threshold voltage and high-speed or with a high-threshold voltage and a low-speed operation. In some cases, where reliability is important, a high-voltage and a low-speed operation is used.
To begin the operation of a semiconductor memory device, a power up voltage is applied. Some circuits may not respond immediately when the power up voltage is first applied and they may only operate after the power source voltage rises to a predetermined level. This delay can cause unstable operation at power-up time. Unstable operation may involve indecision between logic ‘high’ and a logical ‘low’ states. Instability can be caused at power up time if circuitry in a memory device is reset before the power source for the memory has completely stabilized.
An internal reset signal generator can be used to generate an internal reset signal when the power source voltage has stabilized to a predetermined value. This can prevent instability and false signals.
FIG. 1 is a circuit diagram of a prior art internal reset signal generator. The internal rest signal generator shown in FIG. 1 includes a voltage divider 10 for dividing a power source voltage into a predetermined divided voltage, a detector circuit 20 for detecting and amplifying the divided voltage, and a buffer circuit 30 for shaping the output of the detector 20 and outputting control signals.
The voltage divider 10 includes PMOS transistors P11 and P12 connected in series between power source voltage Vdd and node N10. The transistors P11 and P12 are connected to form a diode structure, and a resistance element R10 is connected between the node N10 and ground voltage. The voltage divider 10 divides the power source voltage Vdd into a predetermined voltage and outputs the predetermined voltage to the node N10.
The detector circuit 20 includes an inverter circuit that has, as a common gate input, the output node N11. The detector circuit 20 includes PMOS transistors P21 and P22 and NMOS transistors N21 and N22 connected in series between power source Vdd and ground voltage. The buffer circuit 30 includes an inverter for buffering an output of the detector circuit 20.
The internal reset signal generator shown in FIG. 1 operates as follows: When power Vdd is initially supplied, the power source voltage Vdd rises gradually. As the power source voltage Vdd gradually increases, the voltage of the node N10 rises until it reaches the predetermined voltage established by the voltage division provided by PMOS transistors P11 and P12 and the resistance element R10.
The voltage level of the node N10 maintains a logic ‘low’ state until the power source voltage Vdd becomes stabilized at a predetermined level. The PMOS transistors P21 and P22 are turned on by the voltage at node N10 and the detector circuit 20 outputs a logic ‘high’ signal. An output signal from the detector circuit 20 is inputted to the buffer circuit 30 and is shaped through by the inverter in the buffer circuit 30, to generate reset signal PVCCH. A reset of internal elements is accomplished by the reset signal PVCCH.
When the voltage of node N10 rises to the threshold voltage of NMOS transistors N21 and N22, that is, when the voltage of note N10 rises to the trip voltage, NMOS transistors N21 and N22 operate, the detector circuit 20 inverts a level state of the node N10, and the circuit outputs a logic ‘low’ signal.
The logic ‘low’ signal outputted by detector circuit 20 is inputted to the buffer circuit 30 and is shaped by the inverter in the buffer circuit 30. It generates an internal reset disable signal PVCCH. The reset of internal elements is completed by the internal disable signal PVCCH, and a normal operation is performed.
Such a prior art internal reset signal generator is configured so that when the internal reset signal is generated, all of the circuits requiring an internal reset operation are reset, and then, a reset disable signal is generated.
It is noted that the combination of an internal reset signal and an internal reset disable signal may be considered to be “one signal” that has a logic ‘high’ level and a logic ‘low’ level. Herein, the reset signal and the reset disable signals are described and discussed as being two different and separate signals. Describing the signals in this manner is merely done for convenient in describing and understanding the present invention. Those skilled in the art will understand that the reset signal and reset disable could alternatively be described as being one signal having two periods of different voltage levels.
As the internal operating voltages of devices becomes lower, the voltage difference between a device operating at a high-speed and low-voltage and a device operating at a low-speed and high-voltage becomes greater. Furthermore, in an internal reset signal generator that use an internal power source voltage with no externally supplied voltage, in general, the internal power source voltage cannot reach a value significantly greater than the threshold voltage of an MOS transistor which operates as a high voltage device.
The threshold voltage of a MOS transistor is affected by many variables such as a process condition, temperature, etc. Variations in threshold voltage may cause problems in generating the internal reset disable signal and circuits that employ a high voltage device may not be completely reset. This may cause errors in the operation of a semiconductor memory using such a circuit.